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Dear all,

Is it possible to build a VHDL project in UEStudio. It's not in the standard templates (like c++ or verlilog) but I don't know if it's possible to make it.
I don't see any reason why it should not be possible to create a configuration file for "compiling" VHDL to Intel HEX or any other output file format containing the digital logic for the FPGA or EPLD. Of course there is no standard configuration file because the existing configurations mainly made by users are for programming languages creating software and firmware. But a configuration file is just a set of rules how to build dynamically a makefile which is just like a batch file on execution. So if you often create VHDL projects, it is definitely worth the time needed for creating once a configuration file which later can be quickly used for every VHDL project.
Best regards from Austria
Thank you for your answer. I'm using UE but I cannot make a project in it which recognize functions etc. Therefore I want to switch to Eclipse with the VHDL plugin.

But then I thought maybe I can do the same with UEStudio.

Can you tell me where I can find more information to see if I can make a configuration so it has almost the same functionality as with Eclipse and the VHDL plugin. (I.e. special features of UEStudio)

With kind regards,
It would be more easy for us to help you if you would define what you expect. What are your requirements on an IDE for VHDL coding?

First I think you need a good wordfile for syntax highlighting VHDL. The user-submitted wordfiles page has a link to a wordfile for VHDL. You should search for VHDL also with the forum search because I remember that I helped some other users to adapt their VHDL wordfile to get more help by UE/UES with code folding, highlighting matching braces, auto-indent, etc. Further UE/UES now support a grouped function list. So it is possible to not just see function names in the function list view. With appropriate regular expressions you probably can see in the function list view a tree with sections with 1 or more functions and the "parameters" or "variables" of the functions. I'm not familiar with VHDL, so please forgive me if I wrote here nonsense for VHDL.

If your VHDL projects usually consist of more than 1 VHDL source code file, it would make sense to use Ctags in your projects to build symbol database files to be able to easily jump to a symbol definition in same or another VHDL source file of your project. Ctags natively supports VHDL. The symbol parser of UEStudio can't be used because it does not support language VHDL. But that does not really matter for UES (or UE) as long as Ctags installed with UE/UES builds the symbol database file regularly depending on your settings.

Finally you want to build your VHDL source code files to the output file you want. In UEStudio a configuration file defines the rules how to compile, build or rebuild the source (of various types) to destination output. For writing such a configuration file you need the manuals of your VHDL tool chain. Further it is good practice to start with a template. For example configs\Turbo C Compiler\Application is quite simple and therefore good to use as template. Of course if you know any of the tools (compilers) for which a configuration file exists already, use that tool. Read the comments at top of the existing configuration files to see which variables are by default available. For details on the sections and which commands are available for every section open help of UEStudio and click on tab Index. At top of the index list there are listed the help pages with [...] in the title. These are the help pages you need to understand the sections and commands in the configuration files.

If you need more help, please ask here in the forum or IDM support by email.
4 posts Page 1 of 1