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/L20"VHDL" Nocase Line Comment = -- String Chars = " File Extensions = VHD VHO VHDL TVHD
/Delimiters = ; (	)'<>=:+-/*|&
/Function String = "^(^{signal^}^{constant^}[a-z0-9 ]*:[a-z0-9 ]*^);"
/Function String 1 = "component[a-z0-9 ]*is"
/Function String 2 = "%^(*[a-z0-9 ]*:[a-z0-9 ]*^p[a-z0-9 ]* map[ ]++^)"
/Function String 3 = "%^(architecture [a-z0-9 ]* of [a-z0-9 ]*^) is"
/Function String 4 = "%[a-z0-9 ]*:[ ]++process"
/Function String 5 = "^{function^}^{procedure^}[a-z0-9 ]*"
/Indent Strings = "(" "begin" "then" "loop"
/Unindent Strings = ")" "else" "elsif" "end if"
/Open Fold Strings = "(" "begin" "if" "loop"
/Close Fold Strings = ")" "end process" "end if" "end loop"
/Open Brace Strings = "("
/Close Brace Strings = ")"
/C1"VHDL reserved words"
abs access after alias all and architecture array assert attribute
begin block body buffer bus
case component configuration constant
disconnect downto
else elsif end entity exit
false file for function
generate generic group guarded
if impure in inertial inout is
label library linkage literal loop
map mod
nand new next nor not null
of on open or others out
package port postponed procedure process pure
range record register reject rem report return rol ror
select severity shared signal sla sll sra srl subtype
then to transport true type
unaffected units until use
variable
wait when while with
xnor xor
/C2"VHDL attributes"
active ascending
base
delayed driving driving_value
event
falling_edge
high
image instance_name
last_active last_event last_value left leftof length low
path_name pos pred
quiet
reverse_range right rightof rising_edge
simple_name stable succ
transaction
val value
/C3"VHDL types"
bit bit_vector boolean
character
integer
line
natural
positive
real
signed std_logic std_logic_vector string
text time
unsigned
/C4"VHDL Procedures"
endfile endline
file_close file_open
read readline
write writeline
/C5"VHDL Convertion"
to_integer to_unsigned

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/C3"VHDL strings"
** X" B"

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  component component_name is
  port (
      signal_a : in std_logic; -- 
      signal_b : in std_logic; -- 
      signal_c : out std_logic -- 
    );
  end component;

  u_component_name : component_name
    port map (
      signal_a       => signal_a      ,
      signal_b       => signal_b      ,
      signal_c       => signal_c
    );

  p_signal_a : process ( clk, rst_n )
  begin
    if ( rst_n = '0' ) then
      signal_a_i <= '1';
    elsif rising_edge(clk) then
      signal_a_i <= signal_a;
    end if;
  end process;

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  component component_name is
  port
+ (
    );
  end component;

  u_component_name : component_name
+  port map (
    );

  p_signal_a : process ( clk, rst_n )
+  begin
  end process;

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if blahblahblah then
    blahblahblah
end if
if blahblahblah generate
    blahblahblah
end generate
for blahblahblah generate
    blahblahblah
end generate

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/Close Fold Strings = ")" "end process" "end if" "end loop" "end case" "end generate" "end	process" "end	if" "end	loop" "end	case" "end	generate"

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if () then
...
else
...
end if

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if () then
...
end if

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if condition1 then -- (+) looks beyond line 10 "end if" for a matching end
	if condition2 then -- (+) perfectly working fold
		line_1_start <= '1';
	else
		line_1_start <= '0';
	end if; -- (+) produces unnecessary fold anchor
else
	line_1_start <= '0';
end if; -- (+) produces yet another unnecessary fold anchor

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Procedures [group]
   procedure_1 (parameter)

Process [group]
  name_process ( parameter)

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%[ ^t^b]+procedure[ ^t]+?+

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%[ ^t^b0-9a-z_:]++process[ ^t0-9a-z_]+