Verilog syntax highlighting

GoAWest · Feb 03, 2007#12007-02-03T04:00+00:00

I just moved UE12 to a new PC and had to dig out, copy or reconfig some settings. This included the wordfile, including a Verilog syntax highlight template I created a while ago. I first popped onto this forum to see if I could find a newer/better one but didn't see one (VHDL was the closest). However, a websearch found the one below (Verilog syntax highlighting for UltraEdit, Icarus Verilog for Windows, http://bleyer.org/icarus/) which was more complete than the one I had created myself, so I'm posting it here for others.

Note: tab in the line starting with /Delimiters = must be replaced with a tab character after copying the language definition to a text file in UltraEdit.

----------------------------------------------

/L20"Verilog 1364-2001" Line Comment = // Block Comment On = /* Block Comment Off = */ Block Comment On Alt = (* Block Comment Off Alt = *) String Chars = " File Extensions = V VL VMD
/Delimiters = ! "tab#%&()*+,-/:;<=>@[\]^{|}~
/Function String = "%[^t ]++^(config[^t^p ]+[0-9a-z_]+^)"
/Function String 1 = "%[^t ]++^(module[^t^p ]+[0-9a-z_]+^)[^t^p ]++[(;#]"
/Function String 2 = "%[^t ]++^(^{task^}^{function^}[^t^p ]+[~(;]+^)[^t^p ]++[(;#]"
/Function String 3 = "%[^t ]++^(primitive[^t^p ]+[~(;]+^)[^t^p ]++[(;#]"
/Function String 4 = "begin[^t^p ]++^(:[^t^p ]++[0-9a-z_]+^)"
/Indent Strings = "begin" "case" "fork" "specify" "table" "config"
/Unindent Strings = "end" "endcase" "join" "endspecify" "endtable" "endconfig"
/Open Fold Strings = "module" "task" "function" "generate" "primitive" "begin" "case" "fork" "specify" "table" "config" "`ifdef"
/Close Fold Strings = "endmodule" "endtask" "endfunction" "endgenerate" "endprimitive" "end" "endcase" "join" "endspecify" "endtable" "endconfig" "`endif"
/C1"Keywords"
always and assign automatic
begin buf bufif0 bufif1
case casex casez cell cmos config
deassign default defparam design disable
edge else end endcase endconfig endmodule endfunction endgenerate endprimitive endspecify endtable endtask event
for force forever fork function
generate genvar
highz0 highz1
if ifnone initial inout input instance integer
join
large liblist library localparam
macromodule medium module
nand negedge nmos none nor noshowcancelled not notif0 notif1
or output
parameter pulsestyle_onevent pulsestyle_ondetect pmos posedge primitive pull0 pull1 pullup pulldown
real realtime reg release repeat rcmos rnmos rpmos rtran rtranif0 rtanif1
scalared showcancelled signed small specify specparam strength strong0 strong1 supply0 supply1
table task time tran tranif0 tranif1 tri tri1 tri0 triand trior trireg
use
vectored
wait wand weak0 weak1 while wire wor
xnor xor
/C2"System"
** .
** 'b 'B 'o 'O 'd 'D 'h 'H 'sb 'sB 'so 'sO 'sd 'sD 'sh 'sH 'Sb 'SB 'So 'SO 'Sd 'SD 'Sh 'SH
** $
$async$and$array $async$and$plane $async$nand$array $async$nand$plane $async$nor$array $async$nor$plane $async$or$array $async$or$plane
$bitstoreal
$countdrivers
$display $displayb $displayh $displayo
$dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson $dist_t $dist_uniform
$dumpall $dumpfile $dumpflush $dumplimit $dumpoff $dumpon $dumpportsall $dumpportsflush $dumpportslimit $dumpportsoff $dumpportson $dumpvars
$fclose $fdisplayh $fdisplay $fdisplayf $fdisplayb $ferror $fflush $fgetc $fgets $finish $fmonitorb $fmonitor $fmonitorf $fmonitorh $fopen $fread $fscanf $fseek $fsscanf $fstrobe $fstrobebb $fstrobef $fstrobeh $ftel $fullskew $fwriteb $fwritef $fwriteh $fwrite
$getpattern
$history $hold
$incsave $input $itor
$key
$list $log
$monitorb $monitorh $monitoroff $monitoron $monitor $monitoro
$nochange $nokey $nolog
$period $printtimescale
$q_add $q_exam $q_full $q_initialize $q_remove
$random $readmemb $readmemh $realtime $realtobits $recovery $recrem $removal $reset_count $reset $reset_value $restart $rewind $rtoi
$save $scale $scope $sdf_annotate $setup $setuphold $sformat $showscopes $showvariables $showvars $signed $skew $sreadmemb $sreadmemh $stime $stop $strobeb $strobe $strobeh $strobeo $swriteb $swriteh $swriteo $swrite $sync$and$array $sync$and$plane $sync$nand$array $sync$nand$plane $sync$nor$array $sync$nor$plane $sync$or$array $sync$or$plane
$test$plusargs $time $timeformat $timeskew
$ungetc $unsigned
$value$plusargs
$width $writeb $writeh $write $writeo
/C3"Operators"
!
%
&
*
+
,
-
// /
:
;
<
=
>
?
@
^
{
|
}
~
/C4"Directives"
** `
`accelerate `autoexepand_vectornets
`celldefine
`default_nettype `define `default_decay_time `default_trireg_strength `delay_mode_distributed `delay_mode_path `delay_mode_unit `delay_mode_zero
`else `elsif `endcelldefine `endif `endprotect `endprotected `expand_vectornets
`file
`ifdef `ifndef `include
`line
`noaccelerate `noexpand_vectornets `noremove_gatenames `noremove_netnames `nounconnected_drive
`protect `protected
`remove_gatenames `remove_netnames `resetall
`timescale
`unconnected_drive `undef `uselib
/C5"DelaysParametersEscaped"
#
** \

Mofi · Feb 03, 2007#22007-02-03T20:15+00:00

I have corrected in your post the list of operators. The operator characters are also delimiter characters. So single characters must be specified for highlighting the operators independent on the combination they are used for. And I added the special info about the tab character in the list of delimiters.

I'm only wondering about all those words in /C2 starting with $. In the same color group there is also the substring definition ** $ which means highlight all words starting with a $. So why are additionally all those words starting with $ also listed. I think, they are completely useless as long as ** $ exists in the same color group.

Can you verify that after deleting all the words in /C2 starting with $ those strings in Verilog file are still highlighted with color 2?

Edit on 2017-09-19: Sorted the list of delimiters and simplified the case-insensitive searched UltraEdit regular expressions for finding strings for the function list.

dmk11 · Feb 07, 2007#32007-02-07T02:52+00:00

Mine is similar to the above, but I added the following:

/Open Brace Strings = "{" "(" "["
/Close Brace Strings = "}" ")" "]"

That is useful for matching braces.
Is there an UltraEdit keystroke that will bring me to the matching brace (like % in vi)?

And the Verilog2001 file on this website has a better list of operators: https://www.ultraedit.com//resources/wf/verilog2001.uew

One problem I noticed with this definition is that it doesn't support the new System Verilog syntax.

Example: always @(*)

Mofi · Feb 07, 2007#42007-02-07T13:14+00:00

dmk11 wrote:Is there an UltraEdit keystroke that will bring me to the matching brace?

There is the command Search - Match Brace. You can assign any hotkey to it in the keyboard configuration dialog, command SearchMatchBrace. And there is an option in the syntax highlighting configuration dialog named Enable Auto Brace Matching. Details about the command and the configuration option can be found in help of UltraEdit.

dmk11 wrote:And the Verilog2001 file on this website has a better list of operators.

I have already explained in my first post why I have corrected the list of operators to what you can see now in the first post. All operators are also delimiter characters = separators for words. So the operators list in the Verilog2001 file is too much, because for example >= is interpreted by the syntax highlighting engine as single character word > and single character word =. So it is enough and really correct only to specify the single character operators independent in which combination they are used for in the Verilog file.

dmk11 wrote:One problem I noticed with this definition is that it doesn't support the new System Verilog syntax.
Example: always @(*)

I don't know the Verilog syntax. Can you explain it more detailed. Maybe I can find a solution.

toddm · Feb 08, 2007#52007-02-08T19:50+00:00

dmk11 wrote:always @(*)

I love that feature. No more forgetting to put signals in my sensitivity list.

dmk11 · Mar 09, 2007#62007-03-09T00:23+00:00

Mofi wrote:I don't know the Verilog syntax. Can you explain it more detailed. Maybe I can find a solution.

In regular Verilog, you need to specify individual signals used in an always block.

Example:

Code: Select all

always @(sig1 or sig2 or sig3)

OR

Code: Select all

always @(sig1, sig2, sig3)

In addition to the above, System Verilog also support

Code: Select all

always @(*)

It'll automatically take all the signals used in the always block and assumed it's in the list.

The current syntax definition think of it as the start of a block comment.

wimille · Sep 18, 2017#72017-09-18T18:03+00:00

Hi!

I wanted to update the wordfile to add my own function. However, this does not work. This is what I want to "get":

I have in my file:

Code: Select all

componentA inst_componentA (
[...]
)

componentA inst_componentB (
[...]
)

I want to extract "inst_componentB". Term "inst_" is always the beginning of the sentence.
Can you help me?

Mofi · Sep 19, 2017#82017-09-19T05:37+00:00

Add to the list of function strings as shown in first posted the following line:

Code: Select all

/Function String 5 = "%[^t ]++[a-z_][0-9a-z_]++[^t ]+^(inst_[0-9a-z_]+^)[^t ]++("

% ... start each search at beginning of a line.

[^t ]++ ... find 0 or more tabs or spaces. In other words there can be optionally preceding spaces/tabs.

[a-z_] ... the first character on the line after optional preceding spaces/tabs must be a letter or an underscore.

I assume that Verilog does not allow that a component name starts with a digit like many other languages. UltraEdit runs the regular expressions always case-insensitive. For that reason it is enough to specify just a-z because A-Z is also matched by a-z character class definition.

[0-9a-z_]++ ... find 0 or more digits, letters or underscores to match entire component name.

[^t ]+ ... find 1 or more tabs or spaces after component name.

^(...^) ... tagged group. The string found by the expression inside this tagged group is displayed in the function list. Everything else also found by the entire expression is not listed in function list.

inst_[0-9a-z_]+ ... find the string inst_ with 1 or more digits, letters or underscores appended.

[^t ]++ ... find 0 or more tabs or spaces after instance name. I assume inst means instance.

( ... there must be next an opening parenthesis on the same line.

Please let me know if you want to use for Verilog function list extended features like a grouped function list or a better displayed list of functions, task, modules, ... by using Perl regular expressions instead of UltraEdit regular expressions. There have been some improvements on function list string definitions and display since 2007.

wimille · Sep 19, 2017#92017-09-19T18:42+00:00

Hi Mofi, and thank you very much.
It 's working fine.

I already view this type of syntax (view but not fully understood until now), but what do you mean by Perl regex and new function for Verilog?

Mofi · Sep 20, 2017#102017-09-20T06:18+00:00

I would first discuss once more the UltraEdit regular expression strings as posted by GoAWest more than ten years ago and slightly modified by me without changing the search results. I do not really understand in function string two and three the expression: [~(;]+^)[^t^p ]++[(;#]

The first negative character class definition [~(;]+ means find one or more characters not being an opening round bracket or a semicolon. Therefore this class definition includes also tabs, carriage returns, line-feeds, spaces and hashes.

For that reason [^t^p ]++ does not make sense to me because all tabs, carriage returns, line-feeds and spaces are matched already by previous character class definition and this character class definition matches never any specified whitespace character.

[(;#] means find 1 opening round bracket or semicolon or hash. But all hashes are matched already by [~(;]+. So I doubt that this expression works as expected for function, task and primitive definitions with # instead of ( or ; as end of the definition.

Conclusion, better is perhaps the usage of:

Code: Select all

/Function String = "%[^t ]++^(config[^t^p ]+[0-9a-z_]+^)"
/Function String 1 = "%[^t ]++^(module[^t^p ]+[0-9a-z_]+^)[^t^p ]++[(;#]"
/Function String 2 = "%[^t ]++^(^{task^}^{function^}[^t^p ]+[~(;#]+^)[(;#]"
/Function String 3 = "%[^t ]++^(primitive[^t^p ]+[~(;#]+^)[(;#]"
/Function String 4 = "begin[^t^p ]++^(:[^t^p ]++[0-9a-z_]+^)"
/Function String 5 = "%[^t ]++[a-z_][0-9a-z_]++[^t ]+^(inst_[0-9a-z_]+^)[^t ]++("

Note: I moved the space character in the whitespace character class definitions here and in the other posts from begin to end just for having them in the list according to their code values. This modification has no effect on regular expression search.

Perl instead of UltraEdit regular expressions can be used for searching for strings for the function list since UltraEdit for Windows v13.10 and UEStudio v6.30. The Perl regular expression engine is much more powerful than the UltraEdit regular expression engine.

The Perl regular expression engine supports more than two arguments in an OR expression as used in the function strings below. That reduces the number of searches UltraEdit has to execute on a Verilog file on using a flat function list.

There is the predefined character class \s to match any whitespace character according to Unicode standard which is used in the regular expressions below instead of [^t^p ].

UltraEdit regular expression supports on replace up to nine tagged groups. But on usage of tagged groups in the regular expressions for the function list in the wordfile only the string found by the first tagged group is displayed in the function list. The Perl regular expression engine supports also tagged groups (capturing groups). But the behavior is different on using more than one tagged group in the Perl regular expression search strings in the wordfile. Instead of just displaying the string found by first tagged group, all strings found by all tagged groups are displayed in the function list on using Perl regular expression with a single space between each of the found strings. This difference makes it possible to get displayed a symbol name with its keyword always with 1 space character between. That is useful for a flat function list when the file contains keyword and symbol name with varying whitespaces between because displayed are keyword and symbol name in function list always with one space between.

Here is the function string definition using Perl regular expression for a flat function list:

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/Function String = "^[\t ]*(config)\s+([0-9a-z_]+)"
/Function String 1 = "^[\t ]*(module)\s+([0-9a-z_]+)\s*[(;#]"
/Function String 2 = "^[\t ]*(task|function|primitive)\s+([^(;#]+?)[(;#]"
/Function String 3 = "begin\s*(:)\s*([0-9a-z_]+)"
/Function String 4 = "^[\t ]*[a-z_][0-9a-z_]*[\t ]+(inst_[0-9a-z_]+)[\t ]*\("
/Regexp Type = Perl

Note: UltraEdit for Windows v16.00 and UEStudio v10.00 introduced the tree-style function list also named grouped function list. The default for the function list view is the tree-style list. To use a flat list it is necessary to click with secondary (right) mouse button into the function list view and click in context menu on menu item Flat List.

It is also possible to get the various symbol names displayed in groups. UltraEdit and UEStudio supports the definition of the regular expression (UltraEdit and Perl syntax) search strings in groups. Here is an example using Perl regular expression engine:

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/TGBegin "Beginnings"
/TGFindStr = "begin\s*:\s*([0-9a-z_]+)"
/TGEnd
/TGBegin "Configurations"
/TGFindStr = "^[\t ]*config\s+([0-9a-z_]+)"
/TGEnd
/TGBegin "Modules"
/TGFindStr = "^[\t ]*module\s+([0-9a-z_]+)\s*[(;#]"
/TGEnd
/TGBegin "Functions"
/TGFindStr = "^[\t ]*function\s+([^(;#]+?)[(;#]"
/TGEnd
/TGBegin "Instances"
/TGFindStr = "^[\t ]*[a-z_][0-9a-z_]*[\t ]+inst_([0-9a-z_]+)[\t ]*\("
/TGEnd
/TGBegin "Primitives"
/TGFindStr = "^[\t ]*primitive\s+([^(;#]+?)[(;#]"
/TGEnd
/TGBegin "Tasks"
/TGFindStr = "^[\t ]*task\s+([^(;#]+?)[(;#]"
/TGEnd
/Regexp Type = Perl

It is possible to modify the regular expressions of a grouped function list definition directly in UltraEdit without opening the wordfile at all. Click with secondary (right) mouse button into the function list view and click in context menu on menu item Configuration for opening the dialog window to define and edit the groups and their regular expressions.

It would be also possible to define a group within a group as used for example for C/C++ for functions as one group and for each function two subgroups listing the function parameters and the local variables of the function. I don't know anything about syntax of Verilog and have no sample files to offer a grouped function list with subgroups to build a real tree view.

The disadvantage of this grouped function list definition in comparison to flat list definition is the usage of more regular expression search strings. So UltraEdit/UEStudio needs a bit longer to search for strings in a Verilog file for the function list. However, this disadvantage is most likely not noticeable when the Verilog files are just a few KiB and not dozens or hundreds of MiB.

wimille · Sep 21, 2017#112017-09-21T18:36+00:00

Thanks for this very interesting answer.
I didn't know that it was possible to use Perl regular expression in function list. I better known this type of regex, not so much but a bit better than UE regex.

From all of your explanation, I will be able to update and/or add new functions.