VHDL signal'event vs signal = '1' highlighting

VHDL signal'event vs signal = '1' highlighting

2
NewbieNewbie
2

    Dec 18, 2006#1

    I'm looking for a way to properly highlight the signal'event or any of the many 'parameter qualifiers in VHDL. Currently my wordfile correctly highlights things within single ticks such as '1' but with signal'event and others it highlights until the next signal'event. Has anyone solved this issue ???

    Thanks
    6,675585
    Grand MasterGrand Master
    6,675585

      Re: VHDL signal'event vs signal = '1' highlighting

      Dec 18, 2006#2

      A wordfile for VHDL syntax highlighting is posted at Syntax highlighting wordfile for VHDL.

      You can see there that only the double quote character is specified as String Chars = in the first line. I guess, in your language definition for VHDL either String Chars = is missing or " and ' are defined as string characters. Remove ' from this definition.

      Additionally you should insert in the first line for example between Nocase and String Chars = the keyword DisableMLS (with exactly this spelling!). This keyword disables multi-line string highlighting. Well, I'm not a VHDL programmer, so I don't know if VHDL supports multi-line strings or not.
      Best regards from an UC/UE/UES for Windows user from Austria
      2
      NewbieNewbie
      2

        Dec 18, 2006#3

        Mofi,

        Thanks a LOT the DisableMLS works great, my wife and I have been wanting to visit the Danube river in Austria for a long time now. Maybe some day!

        Greetings from Boston, USA.